An SRAM can save data, which is stored in the static random accessible memory, without a need of refreshing a circuit. Therefore, it is greatly helpful to improve system performance. SRAMs are used by a Level 1 cache and a Level 2 cache in a central processing unit (CPU). To further improve CPU performance, timing paths of the CPU need to be reduced and an external Level 1 SRAM cache or Level 2 SRAM cache with low capacity needs to be integrated. However, as one of the critical timing paths, an SRAM timing path limits improvement of a working frequency of the CPU. At a high level, SRAMs may be classified into two types: synchronous type and asynchronous type. A synchronous SRAM adopts one input clock to start all data processing (such as reading, writing, and deselecting). An asynchronous SRAM, however, does not have clock input and must monitor input to acquire a command from a controller. Upon identifying a certain command, the asynchronous SRAM immediately executes it.
A synchronous SRAM commonly used at present is shown in an electrical schematic diagram in FIG. 1. One timing path of the synchronous SRAM is described in the following with reference to FIG. 1. An address latch 101 latches an input clock signal, and when certain setup time and hold time between the clock signal and an address signal are satisfied, the address latch 101 outputs an internal address signal; a wordline decoder 102 performs logic decoding on the internal address signal; and a sense amplifier 103 is connected to a bitline and an anti-bit line, and amplifies, when a voltage difference between the bitline and the anti-bit line rises to a certain range, data input by a memory cell array 104, and outputs the amplified data.
During implementation of the present invention, the inventor of the present invention finds the prior art has at least the following defects: in an existing synchronous SRAM, an address latch latches an address signal first; for the latch, certain setup time and hold time need to be satisfied before an internal address signal is output; and after being latched, an address is transmitted to an address decoder for address decoding. The address latching performed by the address latch consumes a certain amount of time, which increases running time of a timing path of the synchronous SRAM, thereby reducing a working speed of the synchronous SRAM.